1. Field of the Invention
This invention pertains generally to FPGA resynthesis and remapping and more particularly to in-place resynthesis and remapping techniques for soft error mitigation in FPGAs.
2. Description of Related Art
Modern FPGAs use ever advancing fabrication technologies to achieve higher density at reduced power consumption levels, but at the cost of more vulnerability to a single event upset (SEU), such as caused by supply voltage fluctuations, electromagnetic coupling and environmental radiation. Since an FPGA utilizes memory cells (primarily static random access memory (SRAM)) to implement logic functions and interconnects, the occurrence of a SEU can lead to a permanent impact on the logic function and interconnect, which can only be resolved by reprogramming the FPGA. Although this is not a critical concern for FPGAs used in prototypes, it is an issue that must be addressed when FPGAs are utilized in various system implementations, such as within internet router devices, or other applications which require low failure rates.
In view of the increasing number of FPGA chips which are utilized in deployed systems ranging from internet line cards to enterprise servers, robustness is among the most important design objectives for new FPGA designs. Moreover, while robustness needs to be researched for different design stages of FPGA-based systems, there is also a need for logic design and synthesis that explicitly accounts for and tolerates faults including soft errors.
Robustness in FPGAs has been extensively studied in the literature. Specific FPGA architectures have been developed such as radiation hardened FPGAs from Xilinx and anti-fuse based FPGAs from Actel. Circuit redundancy such as triple modular redundancy (TMR) and quadruple modular redundancy (QMR) have also been proposed.
However, the aforementioned FPGA techniques are accompanied by high overheads in relation to cost, area and/or power, typically with three-times to six-times (˜3× to ˜6×) the amount of overhead in relation to timing, power, and area. The substantial overhead increases necessary to overcome SEUs often renders the devices impractical for use in non-mission critical applications such as communication systems.
Although SEU resilience of an FPGA decreases as fabrication geometry of device technology shrinks, due to lower voltage and smaller charging capacitance, the demand continues for increased logic density.
Accordingly, a need exists for fault tolerant techniques that effectively improves FPGA robustness FPGAs with minimal or no overhead. The present invention fulfills that need and others with minimal overhead impact.